The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Dec. 18, 2019
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Yoram Betser, Mazkeret Batya, IL;

Cliff Zitlaw, San Jose, CA (US);

Stephan Rosner, Campbell, CA (US);

Kobi Danon, Te-Aviv, IL;

Amir Rochman, Tel-aviv, IL;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/1668 (2013.01); G06F 13/4234 (2013.01); G06F 13/4291 (2013.01); G06F 2213/0002 (2013.01); G06F 2213/0004 (2013.01);
Abstract

A nonvolatile memory device can include a serial port having at least one serial clock input, and at least one serial data input/output (I/O) configured to receive command, address and write data in synchronism with the at least one serial clock input. At least one parallel port can include a plurality of command address inputs configured to receive command and address data in groups of parallel bits and a plurality of unidirectional data outputs configured to output read data in parallel on rising and falling edges of a data clock signal. Each of a plurality of banks can include nonvolatile memory cells and be configurable for access by the serial port or the parallel port. When a bank is configured for access by the serial port, the bank is not accessible by the at least one parallel port. Related methods and systems are also disclosed.


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