The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Aug. 06, 2018
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Daniel Arulraj, Austin, TX (US);

Lee Evan Eisen, Round Rock, TX (US);

Graeme Peter Barnes, Cambridge, GB;

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/14 (2006.01); G06F 9/30 (2018.01); G06F 12/02 (2006.01); G06F 9/35 (2018.01); G06F 12/04 (2006.01); G06F 12/06 (2006.01); G06F 9/34 (2018.01);
U.S. Cl.
CPC ...
G06F 12/1441 (2013.01); G06F 9/3004 (2013.01); G06F 9/30007 (2013.01); G06F 9/3012 (2013.01); G06F 9/342 (2013.01); G06F 9/35 (2013.01); G06F 12/00 (2013.01); G06F 12/0223 (2013.01); G06F 12/0284 (2013.01); G06F 12/0292 (2013.01); G06F 12/04 (2013.01); G06F 12/06 (2013.01); G06F 12/0615 (2013.01); G06F 12/1483 (2013.01); G06F 2212/1052 (2013.01);
Abstract

An apparatus and method are provided for comparing regions associated with first and second bounded pointers to determine whether the region defined for the second bounded pointer is a subset of the region defined for the first bounded pointer. Each bounded pointer has a pointer value and associated upper and lower limits identifying the memory region for that bounded pointer. The apparatus stores first and second bounded pointer representations, each representation comprising a pointer value having p bits, and identifying the upper and lower limits in a compressed form by identifying a lower limit mantissa of q bits, an upper limit mantissa of q bits and an exponent value e. A most significant p−q−e bits of the lower limit and the upper limit is derivable from the most significant p−q−e bits of the pointer value. Mapping circuitry is used to map the lower limit mantissas and upper limit mantissas of the first and second bounded pointer representations to a q+x bit address space comprising 2regions of size 2, where n1 is the value of n determined when using the exponent value of the first bounded pointer representation. Mantissa extension circuitry extends the lower limit and upper limit mantissas for each bounded pointer representation to create extended lower limit and upper limit mantissas comprising q+x bits, where a most significant x bits of each extended limit mantissa are mapping bits identifying which region the associated limit mantissa is mapped to. The determination circuitry then determines whether the region for the second pointer is a subset of the region for the first bounded pointer by comparing the extended lower and upper limit mantissas.


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