The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Feb. 21, 2019
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Siddharth Rele, Navi Mumbai, IN;

Shreegopal S. Agrawal, Hyderabad, IN;

Kaustuv Manji, Hyderabad, IN;

Aditya Chaubal, Fremont, CA (US);

Assignee:

XLNX, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/4401 (2018.01); G06F 21/30 (2013.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4401 (2013.01); G06F 15/7825 (2013.01); G06F 21/30 (2013.01);
Abstract

Approaches for configuring a system-on-chip (SOC) include generating component images for components of the SOC. A first component image is for a platform management controller, a second component image is for programmable logic, and a third component image is for a processor subsystem. The plurality of component images are assembled into a programmable device image, and the programmable device image is input to the platform management controller. The platform management controller is booted from the first component image, the programmable logic is configured with the second component image by the platform management controller in executing the first component image, and the processor subsystem is configured with the third component image by the platform management controller in executing the first component image.


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