The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Dec. 20, 2019
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Eran Sharon, Rishon Lezion, IL;

Alex Bazarsky, Holon, IL;

Idan Alrod, Herzliya, IL;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 16/08 (2006.01); G06F 11/10 (2006.01); G11C 13/00 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0634 (2013.01); G06F 3/0679 (2013.01); G06F 11/1068 (2013.01); G11C 13/004 (2013.01); G11C 13/0026 (2013.01); G11C 13/0028 (2013.01); G11C 16/08 (2013.01); G11C 16/26 (2013.01); G11C 2013/0045 (2013.01);
Abstract

Apparatuses, systems, and methods are presented for reading data. A controller may be configured to select a read mode from a plurality of read modes for reading data from a region of a non-volatile memory array. The plurality of read modes may include at least a time-based soft bit read mode. The controller may be configured to apply a set of bias conditions to cells of a region so that bit line currents associated with the cells of the region affect voltages at capacitors associated with the cells of the region. The controller may be configured to, in response to selecting a time-based soft bit read mode, read hard bits and soft bits for a region by sensing capacitor voltages resulting from an applied set of bias conditions, at multiple integration times.


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