The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2021

Filed:

Apr. 03, 2019
Applicant:

The Boeing Company, Chicago, IL (US);

Inventors:

Mark Yao, Irvine, CA (US);

Manuel F. Cabanas-Holmen, Roy, WA (US);

Ethan H. Cannon, Issaquah, WA (US);

Assignee:

THE BOEING COMPANY, Chicago, IL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 29/26 (2006.01); G01R 31/26 (2020.01); G01R 31/27 (2006.01); G11C 7/24 (2006.01); G11C 11/418 (2006.01); G11C 11/419 (2006.01); H01L 27/11 (2006.01); G01R 23/20 (2006.01); G01R 27/28 (2006.01); G01R 31/28 (2006.01); H04B 17/20 (2015.01); H04B 17/336 (2015.01); H04B 3/46 (2015.01); H04B 17/21 (2015.01);
U.S. Cl.
CPC ...
G01R 31/2626 (2013.01); G01R 23/20 (2013.01); G01R 27/28 (2013.01); G01R 29/26 (2013.01); G01R 31/275 (2013.01); G01R 31/2834 (2013.01); G11C 7/24 (2013.01); G11C 11/418 (2013.01); G11C 11/419 (2013.01); H01L 27/1104 (2013.01); H04B 3/46 (2013.01); H04B 17/20 (2015.01); H04B 17/21 (2015.01); H04B 17/336 (2015.01);
Abstract

A test structure for measuring static noise margin (SNM) for one or more static random access memory (SRAM) cells can include a first transistor gate (TG) and a second TG electrically coupled to each SRAM cell. In an implementation, an interconnect between an output of a first inverter and an input of a second inverter of the SRAM cell can be electrically disconnected using a cut off. During operation of the SRAM cell, internal storage nodes within the SRAM cell can be electrically coupled through the first TG and the second TG to, for example, external pins and to a test fixture. Electrical parameters such as voltage can be measured at the internal storage nodes through the external pins and used to calculate SNM of the SRAM cell.


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