The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Aug. 01, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Todd E. Takken, Brewster, NY (US);

Xin Zhang, Yorktown Heights, NY (US);

Yuan Yao, Tarrytown, NY (US);

Andrew Ferencz, Southborough, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/09 (2006.01); H05K 1/11 (2006.01); H05K 1/16 (2006.01); H05K 3/30 (2006.01); H05K 3/40 (2006.01); H01Q 1/24 (2006.01); H01Q 1/28 (2006.01); H01Q 1/50 (2006.01); H01R 12/00 (2006.01); H01L 23/00 (2006.01); H01L 23/12 (2006.01); G06K 7/10 (2006.01); H05K 13/04 (2006.01); H05K 3/36 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0298 (2013.01); H05K 3/366 (2013.01); H05K 13/04 (2013.01); H05K 1/117 (2013.01); H05K 3/403 (2013.01); H05K 2201/0919 (2013.01); H05K 2201/09145 (2013.01);
Abstract

A printed circuit board (PCB) structure and mounting assembly for joining two PCBs. A first PCB has a top and bottom surface faces and a peripheral end face separating the top and bottom surface. The first PCB has one or more conductive wire ends exposed at a surface of the peripheral end face; the exposed conductive wire ends forming multiple separate electrical contacts across the thickness and length of the PEF surface. A second PCB has a top surface face and one or more conductive pads exposed at the top surface at locations corresponding to locations of the multiple electrical contacts. A surface mount solder material is disposed on one or more exposed conductive pads for electrically connecting with corresponding the multiple electrical contacts. The disposed solder material stably joins the PEF surface of the first PCB to the top surface of the second PCB in a relative perpendicular orientation.


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