The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Sep. 06, 2019
Applicant:

Psemi Corporation, San Diego, CA (US);

Inventors:

Kashish Pal, Reading, GB;

John Birkbeck, New Milton, GB;

Assignee:

PSEMI CORPORATION, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/19 (2006.01); H03F 3/193 (2006.01); H03F 1/02 (2006.01); H04B 1/04 (2006.01);
U.S. Cl.
CPC ...
H03F 3/193 (2013.01); H03F 1/0205 (2013.01); H03F 2200/451 (2013.01); H04B 1/04 (2013.01);
Abstract

Various methods and circuital arrangements for biasing gates of stacked transistors of a cascode amplifier are presented, where the amplifier is configured to operate according to different modes of operation. Such circuital arrangements operate in a closed loop with a feedback voltage that is based on a sensed voltage at one or more nodes of a replica circuit of the stacked transistors, the amplifier and the replica circuit biased with same gate voltages. According to one aspect, one gate voltage is adjusted based on a comparison of the feedback voltage with a reference voltage, and other gate voltages are derived by offsetting of the one gate voltage with voltages generated by a current flow through a resistive ladder network.


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