The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Nov. 26, 2019
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Reiko Komiya, Nagoya, JP;

Tatsuo Izumi, Yokkaichi, JP;

Takaya Yamanaka, Yokkaichi, JP;

Takeshi Nagatomo, Yokkaichi, JP;

Karin Takagi, Yokkaichi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/1158 (2017.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); G11C 8/14 (2006.01); G11C 7/18 (2006.01); H01L 27/11556 (2017.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); G11C 7/18 (2013.01); G11C 8/14 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01);
Abstract

A memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer extending through the plurality of first electrode layers in a first direction toward the plurality of first electrode layers from the conductive layer, a first insulating film including a tunneling insulator film, a charge-trapping film and a blocking insulator film, a second electrode layer, and a semiconductor base. The charge-trapping film is spaced along the first direction from the semiconductor base, a distance in the first direction between the charge-trapping film and the semiconductor base is larger than a thickness of the blocking insulator film in a second direction toward the plurality of first electrode layers from the first semiconductor layer.


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