The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Feb. 20, 2020
Applicant:

Purdue Research Foundation, West Lafayette, IN (US);

Inventors:

John K. Lynch, West Lafayette, IN (US);

Pedro P. Irazoqui, West Lafayette, IN (US);

Assignee:

Purdue Research Foundation, West Lafayette, IN (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 11/4091 (2006.01); G11C 7/14 (2006.01); G11C 7/06 (2006.01); G11C 7/08 (2006.01); G11C 7/10 (2006.01); G11C 11/4094 (2006.01); G11C 11/419 (2006.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/065 (2013.01); G11C 7/08 (2013.01); G11C 7/106 (2013.01); G11C 7/1051 (2013.01); G11C 7/14 (2013.01); G11C 11/4091 (2013.01); G11C 11/4094 (2013.01); G11C 11/419 (2013.01); G11C 11/565 (2013.01);
Abstract

An electronic memory array includes a plurality of memory domains, a current controller, and a selector device. Each memory domain includes a plurality of bit cells. The current controller includes a current controller output electrically connectable to said plurality of memory domains and is configured to control a bit cell current. The selector device is electrically connected to the current controller and the plurality of memory domains. The selector device is configured to selectively electrically connect the current controller output to only a select one of said memory domains, such that the current controller controls only the bit cell current of the bit cells of the select memory domain.


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