The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Aug. 11, 2017
Applicant:

Microsoft Technology Licensing, Llc, Redmond, WA (US);

Inventors:

Shankar S. Narayan, Redmond, WA (US);

Ryan S. Haraden, Redmond, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2006.01); G06N 3/04 (2006.01); G06F 7/544 (2006.01); G06F 1/3234 (2019.01); G06N 3/063 (2006.01); G06F 1/3287 (2019.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 1/3243 (2013.01); G06F 7/5443 (2013.01); G06N 3/04 (2013.01); G06N 3/063 (2013.01); G06F 1/3287 (2013.01); G06F 9/3004 (2013.01); G06F 9/3887 (2013.01); G06F 2207/4824 (2013.01);
Abstract

Each processor of the SIMD array performs the computations for a respective neuron of a neural network. As part of this computation, each processor of the SIMD array multiplies an input to a weight and accumulates the result for its assigned neuron each (MAC) instruction cycle. A table in a first memory is used to store which input is fed to each processor of the SIMD array. A crossbar is used to route a specific input to each processor each MAC cycle. A second memory is used to provide the appropriate weight to each processor that corresponds the input being routed to that processor.


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