The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Oct. 25, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Sridhar Subramaniam, San Jose, CA (US);

Hongda Lu, Austin, TX (US);

Kok-Hoong Chiu, Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); G06F 30/396 (2020.01); G06F 1/08 (2006.01); G06F 30/30 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 30/3312 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/396 (2020.01); G06F 1/08 (2013.01); G06F 1/10 (2013.01); G06F 30/30 (2020.01); G06F 30/3312 (2020.01); G06F 30/392 (2020.01); G06F 30/394 (2020.01); G06F 30/398 (2020.01); G06F 2119/12 (2020.01);
Abstract

A method of automatically constructing a hierarchical clock tree for an integrated circuit may include constructing a global clock tree on a first level based on first-level constraints, pushing the global clock tree to partitions on a second level, and generating second-level constraints for the partitions on the second level. The second-level constraints may be included in configuration files that may be generated for the partitions on the second level. The first-level constraints may be included in a first-level configuration file that is user-modifiable. The second-level constraints may include information for replicating multiple instantiated partitions on the second level. The method may further include modifying terminal names and/or configurations after pushdown. The method may further include creating infrastructure to analyze timing of the global clock tree.


Find Patent Forward Citations

Subramaniam, Sridhar. (2021). Hierarchical clock tree construction based on constraints (U.S. Patent No. 11023646). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11023646

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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