The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Oct. 03, 2018
Applicants:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Stmicroelectronics (Rousset) Sas, Rousset, FR;

Inventors:

Stefano Lunghi, Azzate, IT;

Albert Martinez, Bouc Bel Air, FR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 29/00 (2006.01); G06F 21/12 (2013.01); G06F 12/14 (2006.01); G06F 21/72 (2013.01); G06F 21/79 (2013.01); G06F 9/445 (2018.01); G06F 21/14 (2013.01); G06F 21/60 (2013.01); G06F 21/74 (2013.01); H04L 9/06 (2006.01);
U.S. Cl.
CPC ...
G06F 21/121 (2013.01); G06F 9/44573 (2013.01); G06F 12/1408 (2013.01); G06F 21/14 (2013.01); G06F 21/602 (2013.01); G06F 21/72 (2013.01); G06F 21/74 (2013.01); G06F 21/79 (2013.01); H04L 9/0631 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/402 (2013.01); H04L 2209/04 (2013.01);
Abstract

An electronic device includes: a non-volatile memory configured to store data including encrypted data; and a digital circuit. The digital circuit includes: a microprocessor configured to access the non-volatile memory and an internal memory; and a decryption circuit arranged on an interconnect network identifying an internal data path for exchanging the data between the non-volatile memory and the microprocessor, and connected to a memory controller of the non-volatile memory for receiving blocks of data from the non-volatile memory, the decryption circuit being configured to: perform a decryption on the fly of blocks of the data read from the non-volatile memory to obtain read decrypted data; generate first decryption masks corresponding to first blocks of data being read from the non-volatile memory at a given read address; and generate second decryption masks corresponding to second blocks of data to be read from the non-volatile memory at a next estimated read address.


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