The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2021

Filed:

Feb. 13, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Christoph Raisch, Gerlingen, DE;

Marco Kraemer, Sindelfingen, DE;

Donald William Schmidt, Stone Ridge, NY (US);

Bernd Nerz, Boeblingen, DE;

Sascha Junghans, Ammerbuch, DE;

Peter Dana Driever, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/48 (2006.01); G06F 13/24 (2006.01); G06F 12/1009 (2016.01); G06F 9/455 (2018.01);
U.S. Cl.
CPC ...
G06F 13/24 (2013.01); G06F 9/45558 (2013.01); G06F 9/4812 (2013.01); G06F 12/1009 (2013.01);
Abstract

An interrupt signal is provided to a guest operating system. A bus attachment device receives an interrupt signal from a bus connected module with an interrupt target ID identifying a processor assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is blocked from receiving interrupt signals using an interrupt blocking indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor unblocked, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.


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