The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Sep. 23, 2019
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventors:

Masahiro Kobayashi, Tokyo, JP;

Takeshi Ichikawa, Hachioji, JP;

Hirofumi Totsuka, Fujisawa, JP;

Yusuke Onuki, Fujisawa, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H04N 5/361 (2011.01); H01L 27/146 (2006.01); H04N 5/3745 (2011.01);
U.S. Cl.
CPC ...
H04N 5/361 (2013.01); H01L 27/1463 (2013.01); H01L 27/14603 (2013.01); H01L 27/14612 (2013.01); H01L 27/14623 (2013.01); H04N 5/37452 (2013.01);
Abstract

A solid-state imaging device including a plurality of pixels including a photoelectric conversion portion, a charge holding portion accumulating a signal charge transferred from the photoelectric conversion portion, and a floating diffusion region to which the signal charge of the charge holding portion is transferred, wherein the photoelectric conversion portion includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type formed under the first semiconductor region, the charge holding portion includes a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type formed under the third semiconductor region, and a p-n junction between the third semiconductor region and the fourth semiconductor region is positioned deeper than a p-n junction between the first semiconductor region and the second semiconductor region.


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