Fast-converging bit-flipping decoder for low-density parity-check codes

Abstract

Disclosed are devices, systems and methods improving the convergence of a bit-flipping decoder in a non-volatile memory device. An example method includes receiving a noisy codeword, the codeword having been generated based on a parity check matrix of a low-density parity-check code and provided to a communication channel prior to reception by the bit-flipping decoder, and performing a single decoding iteration on the received noisy codeword, the single decoding iteration spanning a plurality of stages. In some embodiments, performing a single decoding iteration includes computing a metric corresponding to a single column of the parity check matrix, flipping at least one bit in the single column upon a determination that the metric exceeds a flipping threshold, computing, subsequent to the flipping, a syndrome as a product of the noisy codeword and the parity check matrix, and updating the flipping threshold upon a determination that the syndrome is not zero.