The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Aug. 02, 2018
Applicants:

Boe Technology Group Co., Ltd., Beijing, CN;

Ordos Yuansheng Optoelectronics Co., Ltd., Inner Mongolia, CN;

Inventors:

Ke Zhao, Beijing, CN;

Guoqing Zhang, Beijing, CN;

Hongwei Gao, Beijing, CN;

Xiaowei Wang, Beijing, CN;

Zhihui Jia, Beijing, CN;

Yan Zong, Beijing, CN;

Longfei Yang, Beijing, CN;

Hongxia Yang, Beijing, CN;

Meili Guo, Beijing, CN;

Weifeng Wang, Beijing, CN;

Pucha Zhao, Beijing, CN;

Zhixin Guo, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3233 (2016.01); H01L 27/32 (2006.01); H01L 51/56 (2006.01); H01L 21/66 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1296 (2013.01); G09G 3/3233 (2013.01); H01L 22/20 (2013.01); H01L 27/3244 (2013.01); H01L 51/56 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0842 (2013.01); G09G 2310/0251 (2013.01); G09G 2310/0262 (2013.01); H01L 2227/323 (2013.01); H01L 2251/562 (2013.01);
Abstract

The present disclosure relates to a method and system for performing aging process on the transistor in the display panel. A method for performing aging process on a transistor in a display panel, comprising: obtaining an initial characteristic curve of the transistor; determining an initial cutoff voltage range of the transistor according to the obtained initial characteristic curve; determining a gate-source voltage and a drain-source voltage required by the transistor according to the initial cutoff voltage range, so as to increase an cutoff voltage range of the transistor; and performing aging process on the transistor according to the determined required gate-source voltage and drain-source voltage.


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