The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 25, 2021
Filed:
May. 27, 2019
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/495 (2006.01); H01L 23/544 (2006.01); H01L 21/304 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 24/96 (2013.01); H01L 21/304 (2013.01); H01L 21/4825 (2013.01); H01L 21/561 (2013.01); H01L 21/565 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/4951 (2013.01); H01L 23/49582 (2013.01); H01L 23/544 (2013.01); H01L 2223/5446 (2013.01);
Abstract
A leadless integrated circuit (IC) package includes a spaced apart plurality of lead terminals on at least two sides of the leadless IC package, and an IC die including a substrate having at least a semiconductor surface including circuitry coupled to bond pads with the bond pads having bonding features thereon. The bonding features are flip chip bonded to the plurality of lead terminals. Mold compound is above the IC die and between adjacent lead terminals. The lead terminals and the substrate both extend out to have exposed surfaces at edges of the leadless IC package, and the lead terminals also provide a back side bondable contact.