Storage device having a memory cell with a variable resistance element, in which voltage applied to a word line of the memory cell is controlled based on voltage of a bit line of the memory cell

Abstract

A storage device includes a first layer extending in a first direction, a second layer extending in a second direction intersecting the first direction, a third layer extending in a third direction intersecting the first and second directions, a first transistor including a first gate electrode electrically connected to the second layer, a first selection transistor having a first end electrically connected to the third layer and a second end electrically connected to the second layer, a first cell including a first element electrically connected between the first and second layers and to a node of the second layer that is between the first gate electrode of the first transistor and the second end of the first selection transistor, and a circuit turning on the first selection transistor to electrically connect the first cell to the third layer during a write operation performed on the first cell.