The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2021

Filed:

Jun. 03, 2019
Applicant:

Wago Verwaltungsgesellschaft Mbh, Minden, DE;

Inventor:

Markus Weidner, Minden, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 13/42 (2006.01); H04L 5/00 (2006.01); H04L 7/00 (2006.01); G06F 1/08 (2006.01); G06F 16/903 (2019.01); G06F 9/38 (2018.01); G05B 19/042 (2006.01); G05B 19/05 (2006.01); G06F 11/16 (2006.01); G05B 23/02 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G05B 19/0428 (2013.01); G05B 19/058 (2013.01); G06F 1/12 (2013.01); G06F 9/3836 (2013.01); G06F 9/3877 (2013.01); G06F 11/1633 (2013.01); G06F 16/903 (2019.01); G05B 23/0237 (2013.01); G05B 2219/14012 (2013.01); G05B 2219/14014 (2013.01); G05B 2219/24008 (2013.01); G05B 2219/24184 (2013.01); G05B 2219/24187 (2013.01);
Abstract

A circuit is provided that has three clock sources, a first processing unit connected to the first clock source, a second processing unit connected to the second clock source, and an input unit. The first processing unit has a first logic circuit and a first memory circuit connected to the first logic circuit, wherein a first set of instructions, which is designed to implement a first control program when executed by the first logic circuit, is stored in the first memory circuit, wherein the first clock source specifies a clock timing of the execution of the first set of instructions. The second processing unit has a second logic circuit and a second memory circuit connected to the second logic circuit, wherein a second set of instructions, which is designed to implement a second control program when executed by the second logic circuit, is stored in the second memory circuit.


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