The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Jan. 28, 2020
Applicant:

Marvell Asia Pte., Ltd., Singapore, SG;

Inventor:

Thomas Kniplitsch, Insheim, DE;

Assignee:

Marvell Asia Pte, Ltd., Singapore, SG;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/00 (2013.01); H04L 12/26 (2006.01); G01R 31/3185 (2006.01); G01R 31/319 (2006.01); G06F 11/22 (2006.01); G06F 21/86 (2013.01); H04L 9/32 (2006.01); H04L 12/40 (2006.01);
U.S. Cl.
CPC ...
H04L 43/0817 (2013.01); G01R 31/31907 (2013.01); G01R 31/318533 (2013.01); G01R 31/318597 (2013.01); G06F 11/2294 (2013.01); G06F 21/86 (2013.01); H04L 9/3226 (2013.01); H04L 12/40 (2013.01);
Abstract

A network device including access and test ports, an interface, and first and second controllers. The interface receives an Ethernet frame transmitted over an Ethernet network to the network device. The Ethernet frame includes bits for testing or debugging the memory-mapped device and is received at the interface based on an output of a host device. The first controller converts the Ethernet frame to a first access frame. The test port receives a diagnostic signal transmitted from the host device to the network device. The second controller converts the diagnostic signal to a second access frame and controls passage of the access frames to the memory-mapped device via the access port. The first controller tests or debugs the memory-mapped device based on data received from a register of the memory-mapped device. The data is written in the register based on the first and second access frames.


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