The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Mar. 28, 2017
Applicant:

Mitsubishi Electric Corporation, Tokyo, JP;

Inventor:

Hitoshi Kurusu, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 1/34 (2006.01); H03F 3/213 (2006.01); H03F 3/60 (2006.01); G01S 7/03 (2006.01);
U.S. Cl.
CPC ...
H03F 1/0211 (2013.01); H03F 1/342 (2013.01); H03F 3/213 (2013.01); G01S 7/032 (2013.01); H03F 2200/129 (2013.01); H03F 2200/267 (2013.01); H03F 2200/451 (2013.01);
Abstract

A current reuse type FET amplifier according to the present invention has a capacitance provided between a drain of a first FET in a first stage and a gate of a second FET in a next stage, electrically separates a gate voltage of the second FET from a drain voltage of the first FET, and includes a control circuit controlling the gate voltage of the first FET and the gate voltage of the second FET so that a variation of a drain current of the second FET and a variation of a drain voltage of the first FET are reduced in accordance with a variation of a saturation current Idss of the FET. Furthermore, the current reuse type FET amplifier according to the present invention uses only a depression mode FET to provide a circuit configuration operable with a positive single power source.


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