The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Dec. 14, 2018
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Joseph Michael Leisten, Cork, IE;

Salvatore Giombanco, Cassaro, IT;

Filippo Marino, Tremestieri Etneo, IT;

Rosario Davide Stracquadaini, San Gregorio di Catania, IT;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 1/42 (2007.01); H02M 1/32 (2007.01);
U.S. Cl.
CPC ...
H02M 1/4225 (2013.01); H02M 1/32 (2013.01);
Abstract

In an example, a system comprises a boost power factor correction (PFC) converter including a thermistor, an inductor, and a transistor coupled to a common node. The system also comprises a PFC controller coupled to the common node. The PFC controller includes a comparator coupled to a threshold voltage source and to a non-control terminal of the transistor; a first flip-flop coupled to the comparator and to a control terminal of the transistor; a zero current detector coupled to the inductor; a timer coupled to the comparator and to the zero current detector; a second flip-flop coupled to the timer and to the control terminal of the transistor; an AND gate coupled to the first and second flip-flops; a third flip-flop coupled to the second flip-flop and to the control terminal of the transistor; and a fourth flip-flop coupled to the AND gate and to the control terminal of the transistor.


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