The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 18, 2021
Filed:
Jun. 21, 2018
Applicant:
Toshiba Memory Corporation, Minato-ku, JP;
Inventor:
Kenichi Murooka, San Jose, CA (US);
Assignee:
Toshiba Memory Corporation, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/249 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/2436 (2013.01); H01L 27/2481 (2013.01); H01L 45/04 (2013.01); H01L 45/1226 (2013.01); H01L 45/146 (2013.01); H01L 45/16 (2013.01);
Abstract
According to one embodiment, a memory device includes a first interconnect group, a second interconnect group, and a memory cell. In the first interconnect group, first interconnects are stacked. The first interconnect group includes first regions in which the first interconnects are formed along a first direction, and a second region in which first contact plugs are formed on the first interconnects. In the second region, the first interconnect group includes a step portion. Heights of adjacent terraces of the step portion are different from each other by the two or more first interconnects.