One-time programmable memory using gate-all-around structures

Abstract

An One-Time Programmable (OTP) memory is built in at least one of nano-wire structures. The OTP memory has a plurality of OTP cells. At least one of the OTP cells can have at least one resistive element and at least one nano-wires. The at least one resistive element can be built by an extended source/drain or a MOS gate. The at least one nano-wires can be built on an isolated structure that has at least one MOS gate dividing nano-wires into at least one first active region and a second active region. The first active region can be doped with a first type of dopant and the second active region can be doped with a first or second type of dopant. The OTP element can be coupled to the first active region with the other end coupled to a first supply voltage line. The second active region can be coupled to a second voltage supply line and the MOS gate is coupled to a third voltage supply line. A plurality of address lines can be decoded into a plurality of wordlines coupled to the second or third voltage supply lines. Another plurality of address lines can be decoded into a plurality of bitlines coupled to the first supply voltage lines. By selecting the proper address lines, a target OTP cell can be selected for programming into another logic state or for reading of its logic state.