The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Dec. 20, 2019
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Noboru Shibata, Kawasaki Kanagawa, JP;

Hironori Uchikawa, Fujisawa Kanagawa, JP;

Taira Shibuya, Fujisawa Kanagawa, JP;

Assignee:

KIOXIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01); G06F 3/06 (2006.01); G11C 16/32 (2006.01); H01L 27/115 (2017.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01); H01L 27/115 (2013.01);
Abstract

A semiconductor memory according to an embodiment includes first and second memory cells, first and second memory cell arrays, first and second word lines, and controller. The first and second memory cell array include the first and second memory cells, respectively. The first and second word lines are coupled to the first and second memory cells, respectively. Data of six or more bits including a first bit, a second bit, a third bit, a fourth bit, a fifth bit, and a sixth bit is stored with the use of a combination of a threshold voltage of the first memory cell and a threshold voltage of the second memory cell.


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