The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

May. 07, 2019
Applicant:

Wenzhou University, Zhejiang, CN;

Inventors:

Pengjun Wang, Zhejiang, CN;

Zhen Li, Zhejiang, CN;

Gang Li, Zhejiang, CN;

Bo Chen, Zhejiang, CN;

Assignee:

Wenzhou University, Zhejiang, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/58 (2006.01);
U.S. Cl.
CPC ...
G06F 7/588 (2013.01);
Abstract

A true random number generator with a dynamic compensation capacity comprises a loop control logic, a shift register, a sensitive amplifier and a load matching unit. The sensitive amplifier comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor, a second NMOS transistor and two NMOS arrays. Each NMOS array comprises a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor and a thirteenth NMOS transistor. The load matching unit comprises a first D flip-flop and a second D flip-flop and is connected at an output terminal and an inverted output terminal of the sensitive amplifier. The true random number generator has the advantages of simple feedback regulation and high robustness.


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