The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2021

Filed:

Jun. 02, 2020
Applicant:

Canon Kabushiki Kaisha, Tokyo, JP;

Inventor:

Hiroyuki Muto, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G03G 15/00 (2006.01); G06K 15/00 (2006.01); H03K 3/00 (2006.01); G03G 15/043 (2006.01); H03K 3/037 (2006.01); G03G 15/04 (2006.01); H03K 7/08 (2006.01); G06K 15/12 (2006.01);
U.S. Cl.
CPC ...
G03G 15/043 (2013.01); G03G 15/04072 (2013.01); G06K 15/1204 (2013.01); H03K 3/037 (2013.01); H03K 7/08 (2013.01);
Abstract

This invention provide a PWM outputting circuit that, from pattern data represented by a plurality of bits representing a pulse width, generates a pulse width modulation signal, wherein the circuit comprises a multi-phase-clock generating circuit which generates a multi-phase clock which is a plurality of clocks of mutually different phases; an edge-pulse generating circuit which, from the pattern data that is inputted, detects a bit position of a rising-edge and a bit position of a falling-edge in the pulse width modulation signal, and generates a rising-edge-pulse and a falling-edge-pulse based on the detection; and an SR latch circuit which, by the rising-edge-pulse being inputted to a set terminal and the falling-edge-pulse being inputted to a reset terminal, generates and outputs the pulse width modulation signal.


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