The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Jun. 11, 2019
Applicant:

Arista Networks, Inc., Santa Clara, CA (US);

Inventors:

Russell Andrew Lowes, Haberfield, AU;

Andrew Bridger, Sydney, AU;

Thomas Dejanovic, Canterbury, AU;

David Charles Ambler Snowdon, Darlinghurst, AU;

Assignee:

ARISTA NETWORKS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/04 (2006.01); H04L 7/033 (2006.01); H04L 7/00 (2006.01); H03L 7/08 (2006.01); H03L 7/085 (2006.01);
U.S. Cl.
CPC ...
H04L 7/042 (2013.01); H03L 7/085 (2013.01); H03L 7/0807 (2013.01); H04L 7/0087 (2013.01); H04L 7/0331 (2013.01);
Abstract

Embodiments of the present disclosure include techniques for generating accurate time stamps. In one embodiment, a first timing reference signal corresponding to a first clock domain is combined with a first clock signal corresponding to a second clock domain to produce a second timing reference signal that includes quantization noise. The second timing reference signal is filtered to remove the quantization noise and generate a filtered timing reference signal. The filtered timing reference signal may be sampled in the second clock domain to obtain a time stamp. In one embodiment, a phase locked loop (PLL) is used as the filter. The PLL may generate first and second ramps that correspond to time. One of the ramps may be sampled to obtain a time stamp, for example.


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