The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Jan. 04, 2021
Applicant:

Realtek Semiconductor Corporation, Hsinchu, TW;

Inventor:

Yu-Che Yang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/085 (2006.01); H03L 7/099 (2006.01); H03L 7/081 (2006.01); G04F 10/00 (2006.01); H03L 7/08 (2006.01);
U.S. Cl.
CPC ...
H03L 7/085 (2013.01); G04F 10/005 (2013.01); H03L 7/081 (2013.01); H03L 7/0802 (2013.01); H03L 7/099 (2013.01); H03L 2207/50 (2013.01);
Abstract

A phase locked device includes a digital controlled oscillator circuit, a clock signal generator circuitry, a time to digital converter circuit, and a logic control circuit. The digital controlled oscillator circuit is configured to generate a first clock signal in response to a plurality of digital codes. The clock signal generator circuitry is configured to generate a plurality of second clock signals according to the first clock signal, and to select a third clock signal and a fourth clock signal from the plurality of second clock signals according to a selection signal, in order to generate an output signal. The time to digital converter circuit is configured to detect a delay difference between the output signal and a reference signal, in order to generate the plurality of digital codes. The logic control circuit is configured to generate the selection signal according to the plurality of digital codes.


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