The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2021
Filed:
Mar. 27, 2020
Applicant:
Seiko Epson Corporation, Tokyo, JP;
Inventor:
Minoru Kozaki, Fujimi-machi, JP;
Assignee:
SEIKO EPSON CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/027 (2006.01); H03K 19/20 (2006.01); H03B 5/36 (2006.01);
U.S. Cl.
CPC ...
H03K 3/027 (2013.01); H03B 5/36 (2013.01); H03K 19/20 (2013.01);
Abstract
Provided is an output circuit including a logic circuit, a capacitor, a buffer circuit, and a driver circuit. When a clock signal is input and an enable signal is active, the logic circuit outputs a clock signal based on the clock signal. The buffer circuit receives a signal that is an output signal of the logic circuit via the capacitor. The driver circuit outputs a clock signal based on a signal that is an output signal of the buffer circuit. The logic circuit sets a signal to the same logic level as an input node of the buffer circuit when the enable signal is inactive.