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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11005033 B1

PDFFull Text
Date of Patent:
May. 11, 2021

Filed:

Jan. 14, 2020

Component semiconductor structure

Applicant:

Tdk-micronas Gmbh, Freiburg, DE;

Inventors:

Martin Cornils, Freiburg, DE;

Maria-Cristina Vecchi, Freiburg, DE;

Assignee:

TDK-Micronas GmbH, Freiburg, DE;

Attorney:

Muncy, Geissler, Olds & Lowe, P.C.

Primary Examiner:

David Vu

Assistant Examiner:

Brandon C Fox

Int. Cl.
CPC ...
H01L 43/06 (2006.01); H01L 43/04 (2006.01); H01L 43/14 (2006.01); H01L 23/00 (2006.01); G01R 33/07 (2006.01); G01R 33/02 (2006.01); H01L 23/488 (2006.01); H01L 27/22 (2006.01); H01L 43/12 (2006.01);
U.S. Cl.
CPC ...
H01L 43/065 (2013.01); G01R 33/0206 (2013.01); G01R 33/072 (2013.01); G01R 33/075 (2013.01); G01R 33/077 (2013.01); H01L 23/488 (2013.01); H01L 24/04 (2013.01); H01L 27/22 (2013.01); H01L 43/04 (2013.01); H01L 43/06 (2013.01); H01L 43/12 (2013.01); H01L 43/14 (2013.01); H01L 2224/02 (2013.01);
Abstract

A component semiconductor structure having a semiconductor layer, which has a front side and a back side, at least one integrated circuit being formed on the front side and a first oxide layer being formed on the back side, a monolithically formed semiconductor body having a top surface and a back surface being provided, and a second oxide layer being formed on the back surface, and the two oxide layers being integrally connected to each other, and a sensor region formed between the top surface and the back surface and having a three-dimensional isotropic Hall sensor structure being disposed in the semiconductor body, the Hall sensor structure extending from a buried lower surface up to the top surface, and at least three first highly doped semiconductor contact regions being formed on the top surface and at least three second highly doped semiconductor contact regions being formed on the lower surface.

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