The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

May. 23, 2017
Applicant:

Wuhan China Star Optoelectronics Technology Co., Ltd., Hubei, CN;

Inventor:

Bo Liang, Guangdong, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 21/308 (2006.01); H01L 29/423 (2006.01); H01L 21/3065 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66757 (2013.01); H01L 21/3086 (2013.01); H01L 27/1218 (2013.01); H01L 27/1266 (2013.01); H01L 29/42384 (2013.01); H01L 29/78603 (2013.01); H01L 29/78618 (2013.01); H01L 29/78696 (2013.01); H01L 21/3065 (2013.01); H01L 27/3244 (2013.01); H01L 27/3262 (2013.01);
Abstract

The present disclosure relates to a manufacturing method of inorganic thin film transistors (TFTs), including: forming a p-type semiconductor layer and a n-type semiconductor layer on a hard substrate in sequence, forming a slot on the p-type semiconductor layer, wherein the slot passes through the n-type semiconductor layer, forming a source and a drain on the n-type semiconductor layer, wherein the source and the drain are respectively configured on two sides of the slot, performing a flip-transferring process to transfer the p-type semiconductor layer, the n-type semiconductor layer, the source, and the drain on a flexible substrate, forming a gate insulation layer and a gate on the p-type semiconductor layer in sequence, forming a flat layer on the gate insulation layer, wherein the flat layer covers the gate. The inorganic TFT is designed to obtain a narrow channel inorganic TFT device, to reduce process requirements, and to reduce costs.


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