The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Feb. 14, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Tak Lee, Hwaseong-si, KR;

Su Bin Kang, Suwon-si, KR;

Ji Mo Gu, Seoul, KR;

Yu Jin Seo, Daejeon, KR;

Byoung il Lee, Seoul, KR;

Jun Ho Cha, Incheon, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11578 (2017.01); H01L 27/11582 (2017.01); H01L 27/11568 (2017.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 21/285 (2006.01); H01L 27/11565 (2017.01); H01L 27/11575 (2017.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28568 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11575 (2013.01); H01L 29/1037 (2013.01); H01L 29/4234 (2013.01); H01L 21/02164 (2013.01); H01L 21/02236 (2013.01); H01L 21/31111 (2013.01); H01L 29/40117 (2019.08);
Abstract

A vertical-type memory device includes a substrate having a cell array region and a connection region disposed adjacent to the cell array region, a plurality of gate electrode layers stacked on the cell array region and the connection region, a plurality of channel structures disposed in the cell array region, a plurality of dummy channel structures disposed in the connection region, and a plurality of slits disposed in the plurality of gate electrode layers in the cell array region. The plurality of gate electrode layers forms a stepped structure in the connection region, the plurality of channel structures penetrates the plurality of gate electrode layers, and the plurality of dummy channel structures penetrates at least one of the plurality of gate electrode layers.


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