The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2021
Filed:
Sep. 03, 2019
Applicant:
Toshiba Memory Corporation, Tokyo, JP;
Inventors:
Masaya Ichikawa, Yokkaichi Mie, JP;
Takashi Sugihara, Yokkaichi Mie, JP;
Kaito Shirai, Nagoya Aichi, JP;
Satoshi Kotomari, Yokkaichi Mie, JP;
Assignee:
TOSHIBA MEMORY CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 27/11582 (2017.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract
A semiconductor chip includes a memory cell array and a wiring layer. The memory cell array includes a plurality of blocks arranged in a first direction along a surface of the semiconductor chip. The wiring layer includes a plurality of first pattern regions at different positions along the first direction, each first pattern region including a different pattern corresponding to one or more of the blocks. The first pattern regions can be used to identify portions of the semiconductor chip during analysis or the like.