The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

May. 03, 2019
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventor:

Jonathan Mark Haswell, San Jose, CA (US);

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/1018 (2016.01); G06F 12/02 (2006.01); G06F 12/1045 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1018 (2013.01); G06F 12/0246 (2013.01); G06F 12/1054 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7203 (2013.01);
Abstract

Memory systems that include NAND flash memory and dynamic random access memory (DRAM) are configured to allow a considerably higher ratio of NAND to DRAM without a significant increase in write amplitude. The NAND includes a logical-to-physical (L2P) table. The DRAM includes a buffer divided into regions, an update table of recently written data and linked lists, one for each region of the buffer linking all items in the update table in that region, the DRAM maintaining a set of linked lists, each identifying all regions with the same number of updates in the update table.


Find Patent Forward Citations

Haswell, Jonathan. (2021). Memory system with configurable nand to dram ratio and method of configuring and using such memory system (U.S. Patent No. 11003587). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/11003587

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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