The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Dec. 17, 2019
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Carlos Cavanna, Toronto, CA;

Reid Copeland, Richmond Hill, CA;

Chad McIntyre, Richmond Hill, CA;

Ali Sheikh, Markham, CA;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2018.01); G06F 9/455 (2018.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3806 (2013.01); G06F 9/30058 (2013.01); G06F 9/30061 (2013.01); G06F 9/322 (2013.01); G06F 9/3848 (2013.01); G06F 9/455 (2013.01); G06F 12/0875 (2013.01); G06F 2212/452 (2013.01);
Abstract

Branch instructions are managed in an emulation environment that is executing a program. A plurality of slots in a Polymorphic Inline Cache is populated. A plurality of entries is populated in a branch target buffer residing within an emulated environment in which the program is executing. When an indirect branch instruction associated with the program is encountered, a target address associated with the instruction is identified from the indirect branch instruction. At least one address in each of the slots of the Polymorphic Inline Cache is compared to the target address associated with the indirect branch instruction. If none of the addresses in the slots of the Polymorphic Inline Cache matches the target address associated with the indirect branch instruction, the branch target buffer is searched to identify one of the entries in the branch target buffer that is associated with the target address of the indirect branch instruction.


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