The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

May. 03, 2019
Applicant:

Dell Products L.p., Round Rock, TX (US);

Inventors:

Shyamkumar T. Iyer, Austin, TX (US);

William Price Dawkins, Lakeway, TX (US);

Kurtis John Bowman, Austin, TX (US);

Jimmy Doyle Pike, Georgetown, TX (US);

Assignee:

Dell Products L.P., Round Rock, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 13/40 (2006.01); G06F 12/10 (2016.01); G06F 9/455 (2018.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0647 (2013.01); G06F 3/0604 (2013.01); G06F 3/067 (2013.01); G06F 3/0659 (2013.01); G06F 9/45558 (2013.01); G06F 12/10 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01); G06F 2009/45583 (2013.01); G06F 2212/657 (2013.01);
Abstract

A memory tiering system includes a data mover device coupling a memory fabric to a processing system. At each of a plurality of different times, the data mover device receives a data access request for data from a computer context provided by the processing system, retrieves the data based on a compute-context-memory-fabric mapping that maps the compute context to the first memory subsystem, and provides the data to the processing system for use with the computer context. If the data mover device determines that the data has been retrieved and provisioning for use with the compute context above a memory tiering frequency, it moves the data from the first memory subsystem to a second memory subsystem in the memory fabric that includes higher performance memory characteristics, and causes the compute-context-memory-fabric mapping to be modified to provide a modified compute-context-memory-fabric mapping that maps the compute context to the second memory subsystem.


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