The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Nov. 26, 2019
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Shamim Ahmed, Tempe, AZ (US);

David Eric Haglan, Tempe, AZ (US);

Assignee:

QUALCOMM INCORPORATED, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/575 (2006.01); G05F 1/59 (2006.01); H04B 1/3827 (2015.01);
U.S. Cl.
CPC ...
G05F 1/575 (2013.01); G05F 1/59 (2013.01); H04B 1/3827 (2013.01);
Abstract

A low-dropout (LDO) regulator and an associated method and apparatus are described. The LDO regulator generally includes a first transistor coupled between an input voltage node and an output voltage node of the LDO regulator. The LDO regulator further includes a first amplifier having an output coupled to a gate of the first transistor, wherein a feedback path couples the output voltage node to an input of the first amplifier. The LDO regulator further includes a second amplifier having an output coupled to an enable input of the first amplifier, wherein a voltage-sensing path couples the input voltage node to an input of the second amplifier. The LDO regulator further includes and a second transistor coupled between the gate of the first transistor and a reference potential node, the output of the second amplifier being coupled to a gate of the second transistor.


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