The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2021

Filed:

Feb. 11, 2019
Applicants:

SK Hynix Inc., Icheon, KR;

Industry-academic Cooperation Foundation, Yonsei University, Seoul, KR;

Inventors:

Woojun Choi, Seoul, KR;

Yongtae Lee, Seoul, KR;

Youngcheol Chae, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/099 (2006.01); H03L 7/089 (2006.01); H03L 7/097 (2006.01); G01K 7/01 (2006.01); H03H 17/02 (2006.01); G11C 11/406 (2006.01);
U.S. Cl.
CPC ...
G01K 7/015 (2013.01); G11C 11/40626 (2013.01); H03H 17/0273 (2013.01); H03L 7/0895 (2013.01); H03L 7/097 (2013.01); H03L 7/0992 (2013.01);
Abstract

A temperature sensor using a poly-phase filter may include: a poly-phase filter suitable for receiving a divided clock, and having passive elements coupled to have one or more negative poles and one or more positive zeros; a comparator suitable for generating a reference clock by comparing potentials of first and second filter voltages outputted from the poly-phase filter; a phase frequency detector suitable for outputting an up or down signal by comparing the phase of the reference clock to the phase of a comparison clock; a current supply unit suitable for supplying and integrating a charge current under control of the up or the down signal; an oscillator suitable for outputting an oscillation signal; a divider suitable for generating the divided clock and the comparison clock; and a buffer suitable for inverting and non-inverting the divided clock and outputting the inverted and non-inverted divided clocks.


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