The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Sep. 28, 2018
Applicant:

Analog Devices, Inc., Norwood, MA (US);

Inventor:

John Ross Wallrabenstein, West Lafayette, IN (US);

Assignee:

Analog Devices, Inc., Wilmington, MA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 21/72 (2013.01); H04L 9/32 (2006.01); H04L 9/08 (2006.01);
U.S. Cl.
CPC ...
H04L 9/3278 (2013.01); G06F 21/72 (2013.01); H04L 9/0861 (2013.01); H04L 2209/12 (2013.01);
Abstract

According to various aspects of the present application, systems and methods are provided for implementing a garbled circuit on a device. Doing so allows the device to perform computations while protecting the computations from being observed or accessed by an adversarial entity. A garbled circuit involves two parties, known as the generator and the evaluator, jointly evaluating a function. Conventionally, a garbled circuit is executed on two different devices in order for the two different parties to jointly calculate the function without each party revealing to the other party private information such as input values to the function. Some embodiments provide for execution of the garbled circuit on a single device by implementing both parties on the device as separate processes. Some embodiments prevent an adversarial entity with physical access to the device from being able to observe calculations performed by the device to evaluate a function.


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