The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Dec. 29, 2017
Applicants:

Bin LI, Chantilly, VA (US);

David Bostedo, Fairfax, VA (US);

Landon J. Caley, Fredricksburg, VA (US);

Nicholas J. Chiolino, Fayetteville, AR (US);

Patrick Fleming, Redondo Beach, CA (US);

David D. Moser, Haymarket, VA (US);

Inventors:

Bin Li, Chantilly, VA (US);

David Bostedo, Fairfax, VA (US);

Landon J. Caley, Fredricksburg, VA (US);

Nicholas J. Chiolino, Fayetteville, AR (US);

Patrick Fleming, Redondo Beach, CA (US);

David D. Moser, Haymarket, VA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/3562 (2006.01); H03K 19/003 (2006.01); H03K 3/356 (2006.01);
U.S. Cl.
CPC ...
H03K 3/35625 (2013.01); H03K 19/0033 (2013.01); H03K 3/356069 (2013.01);
Abstract

A flip-flop circuit is disclosed. The flip-flop circuit includes a single-input inverter, a dual-input inverter, a single-input tri-state inverter, a dual-input tri-state inverter, and two single-event transient (SET) filters. The single-input tri-state inverter receives an input signal D. The dual-input tri-state inverter includes a first input, a second input and an output, wherein the first input receives output signals from the dual-input inverter and the second input receives output signals from the dual-input inverter via the first SET filter. The output of the dual-input tri-state inverter sends output signals to a first input of the dual-input inverter and a second input of the dual-input inverter via the second SET filter. The single-input inverter receives inputs from the dual-input inverter to provide an output signal Q for the flip-flop circuit.


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