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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10998436 B1

PDFFull Text
Date of Patent:
May. 04, 2021

Filed:

Mar. 16, 2017

Semiconductor device

Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Jun Fujita, Chiyoda-ku, JP;

Naoto Kaguchi, Chiyoda-ku, JP;

Fumio Wada, Chiyoda-ku, JP;

Assignee:

MITSUBISHI ELECTRIC CORPORATION, Tokyo, JP;

Attorney:

Xsensus LLP

Primary Examiner:

Laura M Menz

Assistant Examiner:

Khatib A Rahman

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 21/288 (2006.01); H01L 21/3213 (2006.01); H01L 23/00 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78 (2013.01); H01L 21/288 (2013.01); H01L 21/3213 (2013.01); H01L 24/32 (2013.01); H01L 29/456 (2013.01); H01L 29/66348 (2013.01); H01L 29/7397 (2013.01); H01L 2224/32245 (2013.01); H01L 2924/13091 (2013.01);
Abstract

A semiconductor device having high reliability is obtained. A semiconductor device includes a semiconductor substrate, a first gate interconnection, a second gate interconnection, a first metal portion, an insulating member, and a second metal portion. The first gate interconnection and the second gate interconnection are disposed on a main surface of the semiconductor substrate with an interval therebetween. The first metal portion is formed on the first gate interconnection and the second gate interconnection. The first metal portion has a top surface located opposite to the semiconductor substrate at a region between the first gate interconnection and the second gate interconnection. A recess is formed in the top surface. The insulating member fills at least a portion of the recess. The second metal portion extends from an upper surface of the insulating member onto the top surface of the first metal portion.

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