The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Oct. 31, 2019
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Hae Soon Oh, Cheongju-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/16 (2006.01); G11C 16/14 (2006.01); G11C 16/24 (2006.01); G11C 16/08 (2006.01); G11C 16/30 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3445 (2013.01); G11C 16/08 (2013.01); G11C 16/14 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01); G11C 16/30 (2013.01);
Abstract

A memory device includes a memory cell block including a plurality of memory cells. The memory device also includes peripheral circuits configured to perform an erase operation by a gate induce drain leakage (GIDL) method by applying a first erase voltage and a second erase voltage to a source line of the memory cell block. The memory device further includes control logic configured to control the peripheral circuits to sequentially perform an operation of applying the first erase voltage and an operation of applying the second erase voltage during the erase operation, wherein memory cells having a plurality of program states, among the plurality of memory cells, are erased to have a pre-erase state during the operation of applying the first erase voltage.


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