The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Nov. 06, 2019
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jung Hwan Lee, Osan-si, KR;

Jung Mi Ko, Icheon-si, KR;

Ji Hwan Kim, Seoul, KR;

Kwang Ho Baek, Icheon-si, KR;

Young Don Jung, Suwon-si, KR;

Assignee:

SK hynix Inc., Icheon-si Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/12 (2006.01); G11C 16/24 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
G11C 16/24 (2013.01); G11C 7/12 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3427 (2013.01); G11C 8/08 (2013.01);
Abstract

A memory device includes: a memory block, coupled to a plurality of word lines; a peripheral circuit for performing a sensing operation on selected memory cells of the memory block, the select memory cells being coupled to a selected word line of the plurality of word lines; a word line voltage controller for controlling a sensing voltage applied to the selected word line to perform the sensing operation on the selected memory cells and configured to control a pass voltage applied to the selected word line and unselected word lines of the plurality of word lines, coupled to the memory block; and a bit line control signal generator for controlling the peripheral circuit to apply a channel precharge voltage to respective bit lines, coupled to the selected memory cells, while the pass voltage is being applied to the selected word line and the unselected word lines.


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