The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Apr. 15, 2019
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Min Hwan Moon, Seoul, KR;

Seon Ju Lee, Gyeonggi-do, KR;

Jung Chul Han, Seoul, KR;

Assignee:

SK hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G11C 11/56 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G11C 16/16 (2013.01); G06F 3/0604 (2013.01); G06F 3/0652 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01);
Abstract

In a memory controller configured to control a memory device including a plurality of memory blocks, the memory controller comprising: a memory interface configured to exchange data with the memory device; and a pre-program controller configured to perform a read operation on a last page of a program sequence for a plurality of pages in an erase target memory block when the memory device is in an idle state, and perform a pre-program operation on the erase target memory block according to the result obtained by performing the read operation, wherein the erase target memory block is a memory block on which an erase operation is to be performed among the plurality of memory blocks, and wherein the erase operation on the erase target memory block is performed after the pre-program operation is performed.


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