Memory device and method of operating the same

Abstract

A memory device includes a plurality of memory cells each including a switching device and a storage device having a phase change material, a decoder circuit including a first bias circuit inputting a first bias voltage to a selected word line connected to a selected memory cell, a second bias circuit inputting a second bias voltage to a selected bit line, a first selection switching device and a first non-selection switching device connected between the first bias circuit and the selected word line, and a second selection switching device and a second non-selection switching device connected between an adjacent word line and the first bias circuit, a control logic sequentially turning off the first selection switching device and the second non-selection switching device, and a sense amplifier comparing a voltage of the selected word line with a reference voltage to determine data of a read operation.