The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Jun. 26, 2019
Applicant:

Hewlett Packard Enterprise Development Lp, Houston, TX (US);

Inventors:

Sanketh Nalli, Palo Alto, CA (US);

Haris Volos, Palo Alto, CA (US);

Kimberly Keeton, Palo Alto, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/0804 (2016.01); G06F 12/0868 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0238 (2013.01); G06F 12/0804 (2013.01); G06F 12/0868 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/1032 (2013.01); G06F 2212/7203 (2013.01); Y02D 10/00 (2018.01);
Abstract

Examples relate to ordering updates for nonvolatile memory accesses. In some examples, a first update that is propagated from a write-through processor cache of a processor is received by a write ordering buffer, where the first update is associated with a first epoch. The first update is stored in a first buffer entry of the write ordering buffer. At this stage, a second update that is propagated from the write-through processor cache is received, where the second update is associated with a second epoch. A second buffer entry of the write ordering buffer is allocated to store the second update. The first buffer entry and the second buffer entry can then be evicted to non-volatile memory in epoch order.


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