The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2021

Filed:

Oct. 07, 2019
Applicant:

Fujitsu Limited, Kawasaki, JP;

Inventors:

Sota Sakashita, Kawasaki, JP;

Yasunobu Akizuki, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/54 (2006.01); G06F 12/0875 (2016.01);
U.S. Cl.
CPC ...
G06F 9/30196 (2013.01); G06F 9/30029 (2013.01); G06F 9/30043 (2013.01); G06F 9/30189 (2013.01); G06F 9/544 (2013.01); G06F 12/0875 (2013.01);
Abstract

By including a storing device that stores a plurality of memory access instructions decoded by a decoder and outputs the memory access instruction stored therein to a cache memory, a determiner that determines whether the storing device is afford to store the plurality of memory access instructions; and an inhibitor that inhibits, when the determiner determines that the storing device is not afford to store a first memory access instruction included in the plurality of memory access instructions, execution of a second memory access instruction being included in the plurality of memory access instructions and being subsequent to the first memory access instruction for a predetermined time period, regardless of a result of determination made on the second memory access instruction by the determiner, the calculation processing apparatus inhibits a switch of the order of a store instruction and a load instruction.


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