Image sensor, address decoder including clock tree, and image processing system including the image sensor

Abstract

An image sensor includes a pixel array including pixels that are arranged in a matrix and respectively generate pixel signals, a row driver to drive the plurality of pixels row by row, a timing generator to generate a clock signal and address signals, a column driver to generate a plurality of column selection signals sequentially activated in response to the clock signal and the address signals, and a column array to receive the pixel signals through a plurality of column lines, perform an analog-to-digital conversion on the pixel signals, and sequentially output pixel data values through an output buffer. The column driver may include a clock tree including first delay elements and second delay elements to generate a plurality of delay clock signals, and a decoding circuit to generate the plurality of column selection signals.