The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2021

Filed:

Oct. 11, 2019
Applicant:

Honeywell International Inc., Morris Plains, NJ (US);

Inventors:

Brendan Hall, Eden Prairie, MN (US);

Kevin Raymond Driscoll, Maple Grove, MN (US);

Assignee:

Honeywell International Inc., Charlotte, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/173 (2006.01); H04L 12/24 (2006.01); H04L 12/26 (2006.01);
U.S. Cl.
CPC ...
H04L 41/0654 (2013.01); H04L 41/0695 (2013.01); H04L 41/0836 (2013.01); H04L 41/0893 (2013.01); H04L 43/12 (2013.01); H04L 43/50 (2013.01);
Abstract

In an embodiment, a computing node includes a computing circuit, a comparing circuit, and an indicator circuit. The computing circuit is configured to generate a first redundant message that corresponds to, and that is independent of, a source message propagating over a network during at least one time period. The comparing circuit is configured to compare information content of one or more corresponding portions of the source message and the first redundant message during each of the at least one time period to generate a comparison result. And the indicator circuit is configured to indicate whether the source message is valid or invalid in response to the comparison result. For example, such computing node can determine the validity of a redundant result with reduced processing overhead, reduced message delay, and reduced message latency as compared to existing computer nodes.


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